Apple 256K Cache DIMM for Power Macintosh 8500 (and others)

This page describes Apple part number 820-0719-B. In particular, I’m looking at one I just pulled out of a Power Mac 8500/180. My basic question is this: How fast a memory bus speed can this cache DIMM support?

Front of cache DIMM
Back of cache DIMM

(Click on images for 200 dpi versions of the images; about 60K each.)

The chips

This cache DIMM has two 32-pin SOJ parts labelled KM68B261AJ-7. These are Samsung 32K x 8 Bit High-Speed BiCMOS Static RAM" chips. Since this amounts to a total of 64 kilobytes of storage, I suspect this is the tag RAM. Perhaps 32,768 16-bit tags.

There are two other parts, which I am assuming is the data RAM. They are 100-pin surface-mount packages labelled 58LC32K32B2LG-9. I have yet to locate the docs on this part. However, judging from the part number, I’m assuming that they are 32K x 32 bit 9 ns RAM chips. This would give us a total capacity of 32K by 64 bits of ram, or 256KB, which is what Apple claims. Also, the 8500 has a 64-bit data bus, so this all makes sense.

There are no other active components on the DIMM. (I’m skipping the 44 chip resistors and capacitors also on the card.) There are two more sets of solder pads for two more 100-pin chips directly opposite the two that are present; I presume that this means that Apple was considering (or even made) a 512KB cache card, which would presumably use two 64K x 8 bit tag RAM chips. (Followup note: my Dave McGuire has confirmed the existence of a 512KB cache DIMM. No data on its constituent parts, though.)

Analysis

Now, the advertized maximum clock speed of the memory bus in this machine is 50 MHz. That’s a cycle time of 20 ns. So, why use parts that are apparently twice as fast as needed? I suspect that this has something to do with the bus cache lookup cycle. But I don’t have timing diagrams for the machine’s memory bus, so I can only guess.

Taking the smaller-capacity chips to be the tag RAM and the larger chips to be the data, and taking a tag width of 16 bits, that leads to a cache line data width of 128 bits. The 8500 (and other machines built using the same logic board design) can take advantage of pairing of its 168-pin memory DIMMS by interleaving the accesses to paired DIMMS for increased memory bandwidth. Since each DIMM is 64 bits wide, it would seem that one bus cycle can involve two fetches from main RAM to fill a single 128-bit cache line. This could explain the use of cache chips that are capable of operating at 100 MHz.

I should point out that I have no idea if that’s correct. 128 bits strikes me as a moderately narrow cache line. Sun computers using UltraSparc processors, for instance, use a cache line of 512 bits. Of course, the UltraSparc is a 64-bit processor, while the PowerPC 601/604/604e are 32-bit processors. Correcting for that difference, the 8500 cache is just half as wide.

In any event, assuming that the deciding timing is that the cache DIMM must be able to respond to a cache line lookup in 1/2 of the bus cycle time (perhaps a dubious assumption), and assuming that the maximum response time of the whole cache DIMM is no longer than 9 ns (which I consider reasonable, given the lack of any address decode or any other kind of logic outside of the RAM chips), then the DIMM should be able to support bus speeds of up to 55.56 MHz.

Summary

Maybe this is why, on my 8500 with a 225 MHz 604e and a bus speed of 56.25 MHz, I experience crashes every once in a while (infreqent but consistent) while doing certain data-intensive operations that have worked flawlessly for me on other machines. I’ve dropped the clock speed by about 4% to 210 MHz, with a bus speed of 52.5 MHz. We’ll see if that eliminates the crashes.

Follow-up a day later: Yep, that seems to do the trick. I can now ftp large (640 MB) files to my Mac from a local file server over FDDI, I can play streaming MP3s from the Internet with iTunes, I can play QuickTime movies, and I can run backups using Retrospect. All of these things reliably crashed my Mac at the higher bus speed.